1. Field of the Invention
This invention relates in general to computer input/output (I/O) device interfaces, and in particular to a method for data compression during refresh operations for computer displays.
2. Description of Related Art
The use of computers to display high resolution color images and video is well known in the art. The volume of data required to display high resolution color images and video has led to the development of data compression and coding techniques, including the JPEG, MPEG, and P*64 standards. Such techniques are often used when storing graphics/video data on disks or when transmitting graphics/video data between computers. However, few designers have considered the effects of transferring large volumes of uncompressed graphics/video data between a CPU and a video subsystem in a PC or workstation.
Typically, the video subsystem will receive decompressed graphics/video data from the CPU, store the data in a frame buffer, and then transmit the graphics/video data to a RAMDAC for conversion into analog form to control the operation of the monitor. Thereafter, the video subsystem must generate a "refresh" data stream at a fixed rate to re-draw every pixel of the image displayed on the monitor. Refresh operations must be performed at a rate high enough to eliminate image flicker on the monitor. Currently, most monitors require that refresh operations be performed at a rate of 72 Hz or higher.
For high resolution and/or high color depth monitors, such refresh operations involve the transfer of huge amounts of uncompressed data. Moreover, the demands of the refresh operation at high resolution (e.g., greater than 1024.times.768 pixels), high color depth (e.g., greater than 32,000 colors), and high refresh rate (e.g., greater than 70 Hz) on a frame buffer is significant. For example, a monitor capable of displaying 1024.times.768 pixels using 256 colors and having a refresh rate of 72 Hz would require the transfer of 56.6 million bytes of uncompressed data every second for the refresh operations. A monitor capable of displaying 1280.times.1024 pixels using 16 million colors and having a refresh rate of 72 Hz refresh rate would require the transfer of 283.1 million bytes of uncompressed data every second for the refresh operations. Thus, refresh operations can consume a large percentage of the available bandwidth of the frame buffer, e.g., greater than 50%. However, refresh operations cannot be ignored or given a low priority, since failure to perform the refresh operations produces immediately perceptible visual artifacts on the monitor.
Trends in video subsystem design are also increasing the demand for sharing frame buffer ownership between multiple masters, for example, the CPU, a local graphics accelerator, and one or more video controllers. All of these devices compete for bandwidth of the frame buffer, and thus cause scheduling and performance problems. This is true even when the frame buffer is constructed as a double buffer, since the address, control, and data paths are commonly shared between devices. The access contention for the frame buffer and the collisions arising therefrom have a direct effect on graphics/video performance.
One common method of reducing collisions is to increase the amount of memory within each device. The device then signals a priority requirement for control of the frame buffer before its internal memory is fully depleted. If more memory can be used within the device, then it will less frequently require access to the frame buffer. Consequently, there would be greater latitude in scheduling requests for the frame buffer among various devices, thereby resulting in more efficient utilization of idle times.
An additional factor is the miss/hit ratio associated with the operation of the frame buffer. Current memory organizations often require that a miss cycle be performed to open a page of memory in the frame buffer. The miss cycle requires significantly longer access delay (3.times. or 4.times.) than a corresponding hit cycle. When multiple devices access the frame buffer, they often access different regions of memory and therefore generate a higher number of new page accesses resulting in a higher number of miss cycles. In addition, when inadequate buffer levels exist, there is a corresponding increase in the number of miss cycles. Any increase in miss cycles will decrease the total available bandwidth from the frame buffer.
Refresh operations have the additional constraint that the data must be output to the monitor in analog form. This is usually through some form of RAMDAC. The RAMDAC receives the pixel data in predefined bit widths (pixel port width) at a fixed frequency (pixel clock), and then translates the data through color palette RAMs that drive a set of DACs to convert the digital signals to the appropriate analog color levels. As resolution, color depth and refresh rates increase, the demands on the interface between the frame buffer and the RAMDAC become significant.
The impact of these factors is often translated into a wide pixel port operating at high frequency. For example, to operate a monitor capable of displaying 1280.times.1024 pixels using 16 million colors and having a refresh rate of 72 Hz refresh rate would require a 48 bit wide data path interface between a frame buffer and a RAMDAC operating at 65 MHz, or alternatively, a 24 bit data path interface between a frame buffer and a RAMDAC operating at 130 MHz. If address, control, and power pins are factored in, the interface may require between 50 and 100 package pins on an ASIC operating at between 65 MHz and 130 MHz.
All of these issues make the refresh operation an attractive candidate for performance enhancing design techniques. Moreover, the overhead incurred in refresh operations will undoubtably become more significant as resolution, color depth, and refresh rates continue to increase. Thus, there is a need in the art to reduce the impact of refresh operations, which in turn, would produce lower device costs and improved system performances.